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1 of 15 111901 features real-time clock (rtc) with fully compatible 1-wire ? microlan interface uses the same binary time/date representation as the ds2404 but with 1 second resolution clock accuracy 2 minutes per month at 25c programmable interrupt output for system wakeup communicates at 16.3kbits per second unique, factory-lasered and tested 64-bit reg- istration number (8-bit family code + 48-bit serial number + 8-bit crc tester) assures ab- solute traceability because no two parts are alike 8-bit family code specifies device communi- cation requirements to bus master built-in multidrop controller ensures com- patibility with other microlan products operates over a wide v dd voltage range of 2.5v to 5.5v from -40c to +85c low power, 200na typically with oscillator running compact, low cost 6-pin tsoc surface mount package pin assignment 6-pin tsoc package top view 1 2 3 6 5 4 side view see mech. drawings section pin description pin 1 gnd pin 2 1-wire pin 3 int pin 4 v dd pin 5 x1 pin 6 x2 ordering information DS2417p 6-pin tsoc package DS2417p/t&r tape & reel of DS2417p DS2417x chip scale pkg., tape & reel description the DS2417 1-wire time chip with interrupt offers a simple solution for stor ing and retrieving vital time information with minimal hard ware. the DS2417 contains a uni que lasered rom and a real-time clock/calendar implemented as a bi nary counter. only one pin is required for communication with the device. utilizing a backup energy source, the data is nonvolatile and allows fo r stand-alone operation. the DS2417 features can be used to add functions su ch as calendar, time and date stamp, and logbook to any type of electronic device or embedded application that uses a microcontroller. overview the DS2417 has two main data com ponents: 1) 64-bit lasered rom, and 2) real-time clock counter (figure 1). the real-time clock utilizes an on-chip oscillator that is connected to an external 32.768khz crystal. the hierarchical structure of the 1-wire prot ocol is shown in figure 2. the bus master must first provide one of four rom function commands: 1) read rom, 2) ma tch rom, 3) search rom, 4) skip rom. the protocol for these rom functions is de scribed in figure 7. after a rom function command DS2417 1-wire time chip with interrupt www.maxim-ic.com
DS2417 2 of 15 is successfully executed, the real-time clock functions become accessible and the master may then provide one of the real-time clock function commands. the protocol for these commands is described in figure 5. all data is read and written least significant bit first. detailed pin description pin symbol description 1 gnd ground pin 21-wire data input/output open drain. 3 int interrupt pin open drain. 4v dd power input pin . 2.5v to 5.5v. 5, 6 x1, x2 crystal pins. connections for a standard 32.768kh z quartz crystal, epson part number c-002rx or c-004r (be sure to request 6pf load capacitance). note: x1 and x2 are very high impedance nodes. it is recommended that they and the crystal be guard-ringed with ground and that high frequency signals be kept away from the crystal area. see figure 10 and application note 58 for de- tails. block diagram figure 1 x1 x2 32.768 khz osc./divider 1-wire rom control function 64-bit rom lasered clock function control rtc counter (32-bit) oscillator control v dd read/write buffer 1 hz int. generator int\ 64-bit lasered rom each DS2417 contains a unique rom code that is 64 b its long. the first eight bits are a 1-wire family code. the next 48 bits are a unique serial number. the last eight bits are a crc of the first 56 bits. (see figure 3.) the 1-wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the dallas semiconductor 1-wi re cyclic redundancy check is ava ilable in the book of ds19xx ibutton ? standards. the shift register bits are initialized to ze ro. then starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th bit of th e serial number has been entered, the shift register contains the crc value. shifting in the eight bits of crc should return the shift register to all zeros. the int
DS2417 3 of 15 64-bit rom and rom function contro l section allow the DS2417 to operate as a 1-wire device and follow the 1-wire protoc ol detailed in the section "1-wire bus system". hierarchical structure for 1-wire protocol figure 2 DS2417 command level available commands data fields affected 1-wire bus other devices bus master DS2417 specific function commands (see figure 5) write clock read clock rtc counter, device control rtc counter, device control read rom match rom search rom skip rom 64-bit rom 64-bit rom 64-bit rom n/a 1-wire rom function commands (see figure 7) 64-bit lasered rom figure 3 msb lsb 8-bit crc code 48-bit serial number 8-bit family code (27h) msb lsb msb lsb msb lsb 1-wire crc generator figure 4 r x 2 x 1 x 0 x 8 x 7 x 6 x 5 x 4 x 3 8th stage 7th stage 6th stage 5th stage 4th stage 3rd stage 2nd stage 1st stage s input data polynomial = x 8 + x 5 + x 4 + 1
DS2417 4 of 15 timekeeping a 32.768khz crystal oscillator is used as the time base for the real-time clock counter. the oscillator can be turned on or off under software control. the osc illator must be on for the re al-time clock to function. the real-time clock counter is double buffered. this allows the master to read time without the data changing while it is being read. to accomplish this, a snapshot of the counter data is transferred to a read/write buffer, which the user accesses. device control byte the DS2417 can generate interrupt pulses to trigger activities that have to occur at regular intervals. the selection of this interval and the on/off control of the 32.768khz crystal oscillator are done through the device control byte. this byte can be read and written through the clock function commands. device control byte 76543210 ie is2 is1 is0 osc osc 0 0 bit 0 - 1 0 no function bits 0 and 1 are hard-wired to read all 0?s. bit 2 - 3 osc oscillator enable/disable these bits control/report whether the 32.768khz crystal os cillator is running. if the oscillator is running, both osc bits will read 1. if the oscillator is turned off these bits will all read 0. when writing the device control byte both occurrences of the osc bit s hould have identical data. otherwise, the value in bit address 3 (bold) takes precedence. bit 4 - 6 is interval select these bits determine the time between interrupt pulses. the values available are shown below. is2 is1 is0 interrupt interval 0001s 0014s 0 1 0 32s = 0.53 min. 0 1 1 64s = 1.07 min. 1 0 0 2048s = 34.13 min. 1 0 1 4096s = 68.27 min. 1 1 0 65536s = 18.20 hours 1 1 1 131072s = 36.41 hours bit 7 ie interrupt enable this bit controls whether the interrupt pulse will be generated at the selected interval. to enable interrupts this bit needs to be 1.
DS2417 5 of 15 real-time clock the real-time clock is a 32-bit binary counter. it is incremented once per second. the real-time clock can accumulate 136 years of seconds before rolling over. time/date is represented by the number of seconds since a reference point, which is determined by the user. for example, 12:00 a.m., january 1, 1970 could be a reference point. clock function commands the ?clock function flow chart? (figure 5) describes the protocols necessary for accessing the real-time clock. with only four bytes of real-time clock and one control by te the DS2417 does not provide random access. reading and writing always starts with the device control byte followed by the least significant byte of the time data. read clock [66h] the read clock command is used to read the device control byte and the contents of the real-time clock counter. after having received the most significan t bit of the command code the device copies the actual contents of the real-time clock counter to the read/wr ite buffer. now, the bus master reads data beginning with the device control byte followed by the least significant byte through the most significant byte of the real-time clock. after this the bus master may continue reading from the DS2417. the data received will be the same as in the first pass through the command flow. the read clock command can be ended at any point by issuing a reset pulse. write clock [99h] the write clock command is used to set the real-time clock counter and to write the device control byte. after issuing the command, the bus master writes fi rst the device control byte, which becomes immedi- ately effective. after this the bus master sends the least significant byte through the most significant byte to be written to the real-time clock counter. the new time data is copied from the read/write buffer to the real-time clock counter and becomes effective as the bus master ge nerates a reset pulse. if enabled, an interrupt pulse will be generated either immediately or delayed, depending on the actual time and the se- lected interval duration (see figure 11). if the osc illator is intentionally stoppe d the real-time clock coun- ter behaves as a four-byte nonvolatile memory.
DS2417 6 of 15 clock function command flow chart figure 5 master tx control function command 66h read clock ? y n bus master tx reset ? n y n bus master tx reset ? DS2417 copies rtc counter to r/w buffer 99h write clock ? n y y n bus master tx reset ? bus master tx ls byte (7:0) bus master tx next byte (15:8) bus master tx next byte (23:16) bus master tx ms byte (31:24) bus master tx device control byte DS2417 copies r/w buffer to rtc counter DS2417 tx presence pulse bus master rx next byte (15:8) bus master rx next byte (23:16) bus master rx ms byte (31:24) bus master rx ls byte (7:0) bus master rx device control byte y
DS2417 7 of 15 hardware configuration figure 6 rx tx open drain port pin 5 a typ. DS2417 1-wire port rx = receive tx = transmit bus master v pup data rx tx mosfet 100 5 k typ. 1-wire bus system the 1-wire bus is a system, which has a single bus master and one or more slaves. in all instances the DS2417 is a slave device. the bus master is typically a microcontro ller. the discussion of this bus system is broken down into three topics: hardware configuration, transac tion sequence, and 1-wire signaling (signal types and timing). a 1-wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. for a more detailed protocol description, refer to chapter 4 of the book of ds19xx ibutton standards. hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open drain or 3-state outputs. the 1-wire input of the DS2417 is open drain w ith an internal circuit equivalent to that shown in figure 6. a multidrop bus consists of a 1-wire bus with multiple slaves attached. the 1-wire bus has a maximum data ra te of 16.3kbits per second and require s a pullup resistor of approxi- mately 5k . the idle state for the 1-wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset. since the DS2417 gets all its energy for operation through its v dd pin it will not perform a power-on reset if the 1-wire bus is low for an extended time period. transaction sequence the protocol for accessing the DS2417 vi a the 1-wire port is as follows: initialization rom function command clock function command
DS2417 8 of 15 initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence con- sists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the DS2417 is on the bus and is ready to operate. for more details, see the ?1-wire signaling? section. rom function commands once the bus master has detected a presence, it can issue one of the four rom function commands that the DS2417 supports. all rom function commands ar e eight bits long. a list of these commands follows (refer to flowchart in figure 7): read rom [33h] this command allows the bus master to read the DS2417?s 8-bit family code, unique 48-bit serial num- ber, and 8-bit crc. this command should only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-and result). the re sultant family code and 48-bit serial number read by the master will be invalid. match rom [55h] the match rom command, followed by a 64-bit rom sequence, allows th e bus master to address a spe- cific DS2417 on a multidrop bus. only the DS2417 that exactly matches the 64-bit rom sequence will respond to the following clock function command. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1- wire bus or their 64-bit rom codes. the search rom command allows the bus master to use a process of elimination to identify the 64-bit rom codes of all slave devices on the bus. the search rom process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the de- sired value of that bit. the bus master performs this three-step routine on each bit of the rom. after one complete pass, the bus master knows the 64-bit rom code of one device. additional passes will identify the rom codes of the remaining devices. see chap ter 5 of the book of ds19xx ibutton standards for a comprehensive discussion of a search rom, including an actual example. skip rom [cch] this command can save time in a single drop bus system by allowing the bus master to access the clock functions without providing the 64-b it rom code. if more than one slave is present on the bus and, for example, a read command is issued following th e skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously ( open-drain pulldowns will produce a wired-and result).
DS2417 9 of 15 rom functions flow chart figure 7 f0h search rom command ? DS2417 tx bit 0 DS2417 tx bit 0 master tx bit 0 bit 0 match ? DS2417 tx bit 1 DS2417 tx bit 1 master tx bit 1 bit 1 match ? DS2417 tx bit 63 DS2417 tx bit 63 master tx bit 63 bit 63 match ? master tx control function command 33h read rom command ? DS2417 tx serial number 6 b y tes DS2417 tx crc b y te DS2417 tx family code 1 b y te match rom 55h command ? bit 0 match ? bit 1 match ? bit 63 match ? master tx bit 1 master tx bit 0 n y n y nn y nn nn y y y y y y ( see figure 5 ) master tx rom function command master tx reset pulse DS2417 tx presence pulse cch skip rom command ? n y n master tx bit 63
DS2417 10 of 15 1?wire signaling the DS2417 requires strict protocols to ensure data integrity. the protoc ol consists of four types of sig- naling on one line: reset sequence with reset puls e and presence pulse, write 0, write 1, and read data. except for the presence pulse the bus master initiates all these signals. the initialization sequence required to begin any co mmunication with the DS2417 is shown in figure 8. a reset pulse followed by a presence pulse indicates the DS2417 is ready to send or receive data. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 s). the bus master then releases the line and goes into receive mode (rx). the 1-wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on the data line, the DS2417 waits (t pdh , 15s to 60s) and then transmits the presence pulse (t pdl , 60s to 240s). initialization procedure ?reset and presence pulses? figure 8 resistor master DS2417 master rx "presence pulse" 480 s t rstl < * 480 s t rsth < ** 15 s t pdh < 60 s 60 t pdl < 240 s master tx "reset pulse" v pullup v pullup min v ih min v il max 0v t rsth t rstl t pdh t pdl t r * in order not to mask interrupt signalin g by other devices on the 1-wire bus t rstl + t r should al- ways be less than 960 s. ** includes recovery time read/write time slots the definitions of write and read time slots are illustrated in figure 9. the master initiates all time slots by driving the data line low. the falling edge of the data line synchronizes the DS2417 to the master by triggering an internal delay circuit. during write time slots, the delay circuit determines when the DS2417 will sample the data line. for a read data time slot, if a ?0? is to be transmitted, the delay circuit determines how long the DS2417 will hol d the data line low. if the data bit is a ?1?, the DS2417 will not hold the data line low at all.
DS2417 11 of 15 read/write timing diagram figure 9 write-one time slot 15s (od: 2s) 60s (od: 6s) DS2417 sampling window v pullup v pullup min v ih min v il max 0v t slot t rec t low1 60 s t slot < 120 s 1 s t low1 < 15 s 1 s t rec < resistor master write-zero time slot 15s resistor master (od: 2s) DS2417 60s t low0 sampling window (od: 6s) 60 s t low0 < t slot < 120 s 1 s t rec < v pullup v pullup min v ih min v il max 0v t slot t rec
DS2417 12 of 15 read/write timing diagram (continued) figure 9 read-data time slot resistor master DS2417 master sampling window 60 s t slot < 120 s 1 s t lowr < 15 s 0 t release < 45 s 1 s t rec < t rdv = 15 s t su < 1 s v pullup v pullup min v ih min v il max 0v t slot t rec t lowr t su t rdv t release crystal placement on pcb figure 10 x2 guard ring on signal plane plane beneath local ground signal plane or on other side of pcb crystal pads gnd x1 1-wire v dd int\
DS2417 13 of 15 interrupt timing figure 11 time = 122 s t interval t pulse t latency v int case a: latency < 0.5 t interval case b: 0 < latency < t interval time = 122 s t interval t pulse t latency v int the latency depends on the selected interrupt interval (is0 to is2 settings) and the contents of the rtc counter at the time of writing the device control byte. in case a, the flip-flop that determines the interval duration is reset and toggles before half of the interval time is over. in case b, this flip-flop is set that generates an immediate interrupt pulse; the latency, therefore, can be up to one full interval duration. if enabled, the interrupt pulse may also be triggered while reading from or writing to the control byte.
DS2417 14 of 15 absolute maximum ratings* voltage on 1-wire to ground -0.5v to +7.0v operating temperature range -40c to +85c storage temperature range -55c to +125c soldering temperature see j-std-020a specification * this is a stress rating only and f unctional operation of the device at these or any other conditions above those indicated in the opera tion sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (v pup = 2.5v to 6.0v; v dd = 2.5v to 5.5v, -40c to +85c) parameter symbol min typ max units notes logic 1 v ih1 2.2 6.0 v 1, 11 logic 0 v il1 -0.3 tbd v 1, 6 output logic low @ 4ma v ol1 0.4 v 1 output logic high v oh1 v pup v 1, 3 input load current i l1 5 a4 interrupt sink current @ 0.4v i int3 5ma9 operating current (osc. on) i dd3 250 na 2, 9 quiescent current (osc. off) i ddq3 50 na 2, 8, 9 interrupt sink current @ 0.4v i int5 10 ma 10 operating current (osc. on) i dd5 450 na 2, 10 quiescent current (osc. off) i ddq5 100 na 2, 8, 10 capacitance (t a = 25c) parameter symbol min typ max units notes capacitance 1-wire c in 50 pf ac electrical characteristics (v pup = 2.5v to 6.0v; v dd = 2.5v to 5.5v, -40c to +85c) parameter symbol min typ max units notes time slot t slot 60 120 s write 1 low time t low1 115 s13 write 0 low time t low0 60 120 s read low time t lowr 115 s13 read data valid t rdv 15 s12 release time t release 01545 s read data setup t su 1 s5 recovery time t rec 1 s reset high time t rsth 480 s reset low time t rstl 480 960 s7 presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s
DS2417 15 of 15 notes: 1. all voltages are referenced to ground. 2. measured with outputs open. 3. v pup = external pullup voltage. 4. input load is to ground. 5. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 s of this falling edge. 6. under certain low voltage conditions v il1max may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 7. the reset low time (t rstl ) should be restricted to a maximum of 960 s, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. 8. when v dd ramps up, the oscillator is always off. 9. at v dd = 3v 10% 10. at v dd = 5v 10% 11. v ih1 has to be v dd ? 0.3v or higher. 12. the optimal sampling point for the master is as close as possible to the end time of the 15s t rdv period without exceeding t rdv . for the case of a read-one time slot, this maximizes the amount of time for the pull-up resistor to recover to a high level. for a read-zero time slot, it ensures that a read will occur before the fastest 1-wire device(s) release the line. 13. the duration of the low pulse sent by the master should be a minimum of 1s with a maximum value as short as possible to allow time for the pull-up resistor to recover the line to a high level before the 1-wire device samples in the case of a write-one time or before the master samples in the case of a read-one time.

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